Софт-Архив

Clock generator

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Описание

Clock generator - Amtech Patent Licensing Corporation

Hane, Roberts, Spiecens & Cohen

What is claimed is:

1. A clock generator for establishing working clock pulses occurring for constant increments in a scan path of a scanner which cyclically sweeps over a record medium at a non-constant velocity, said generator comprising means for generating a fiducial pulse at least once per cycle of sweep, frequency synthesizer means responsive to the fiducial pulses for generating radio-frequency clock pulses having a frequency greater than the fiducial pulses, and in synchronization therewith, storage means for storing a plurality of count values, each of said count values being associated with a given increment along the scan path, working clock pulse generator means, including counter means for counting the radio-frequency clock pulses, for emitting a working clock pulse each time the counter means has counted a count value received by the working clock pulse generator means, and means responsive to the working clock pulses for sequentially transmitting the count values stored in said storage means to said working clock pulse generator means.

2. The apparatus of claim 1 wherein said working clock pulse generator means includes a programmable down counter which is decremented for each received radio-frequency clock pulse, which emits a working clock pulse when decremented to a given value, and which is programmed with a count value from said storage means in response to the occurrence of a working clock pulse.

3. The apparatus of claims 1 or 2 wherein the scanner comprises a reciprocally rotating mirror and a laser beam means directed toward said mirror and said means for generating the fiducial pulses includes a photoelectric means.

4. The apparatus of claim 3 wherein said photoelectric means comprises a photoelectric device for emitting a pulse signal each time the laser beam impinges thereon and means connected to said photoelectric device for emitting a fiducial pulse for each two pulse signals emitted by said photoelectric device.

5. The apparatus of claim 1 wherein said frequency synthesizer means includes means for emitting a start of scan signal for each of the fiducial pulses and said storage means includes a memory having a plurality of addressed storage locations for storing the count values and a recycable address generator means for sequentially generating the addresses of the storage locations in response to the working clock pulses, each of the start of scan signals initiating a new cycle of said address generator means.

6. The apparatus to claim 5 wherein said synthesizer means further includes means for controllably varying the time of occurrence of the start of scan signal during cycle of the scanner.

7. The apparatus of claim 3 wherein said frequency synthesizer means includes means for emitting a start of scan signal for each of the fiducial pulses and said storage means includes a memory having a plurality of addressed storage locations for storing the count values and a recyclable address generator means for sequentially generating the addresses of the storage locations in response to the working clock pulses, each of the start of scan signals initiating a new cycle of said address generator means.

8. The apparatus of claim 7 wherein said synthesizer means further includes means for controllably varying the time of occurrence of the start of the scan signal during cycle of the scanner.

9. The apparatus of claim 8 wherein said means for controllably varying the time of occurrence of the start of the scan signal includes a presettable pulse counter for counting pulses derived from the radio-frequency clock pulses.

Description:

BACKGROUND OF THE INVENTION

This invention pertains to clock generators and, more particularly, to clock generators which are driven by a mechanically oscillating member.

In many optical scanning and recording systems, there is used a planar mirror which reciprocally rotates about an axis in its plane through a relatively small displacement angle so that a light beam fed to the mirror will trace a scan line on a record medium. For high resolution work, it is necessary to divide the scan line into constant length increments per unit time. Because of the oscillatory nature of the mirror rotation, its velocity is not linear and is, in fact, sinusoidal. Therefore, if one used a constant frequency clock to generate the pixels of the scan line, these pixels would not be uniformly spaced and distortion would be present in any image.

SUMMARY OF THE INVENTION

It is accordingly a general object of the invention to provide a clock generator which generates clock pulses which occur for constant length increments in the scan path of a variable velocity scanning device.

Briefly, the invention contemplates such a clock generator for generating working clock pulses occurring at constant length increments in the scan path of a scanner which cyclically sweeps over a record medium at a nonconstant velocity. The generator includes means for generating a fiducial pulse at least once per cycle of sweep. A frequency synthesizer means is responsive to the fiducial pulses for generating radio frequency clock pulses. The radio frequency clock pulses have a frequency greater than the frequency of the fiducial pulses and are in syncronization with these pulses. There is further provided storage means for storing a plurality of count values. Each of these count values is associated with a given length increment along the scan path. A working clock pulse generating means includes a counter means for counting the radio frequency clock pulses and emits a working clock pulse each time the counter means has counted a count value received by the working clock pulse generator means. Finally means responsive to the working clock pulse sequentially transmit the count values stored in the storage means to the working clock pulse generator means.

It should be noted that if all the count values are the same, then the working clock pulses would occur at a constant frequency. However, by making the count values functions of the sinusoidal velocity, then it is seen that the working clock pulses will occur at a frequency proportional to a sinusoid and therefore at constant length increments of sweep of the scanner.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, the features and advantages of the invention will be apparent from the following detailed description when read in conjunction with the accompanying drawing which shows the presently preferred embodiment of the invention.

In the drawing:

FIG. 1 is a block diagram of a laser scanning system incorporating the invention; and

FIG. 2 is a waveform showing the angular displacement of an oscillating mirror about a home position as a function of time.

DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INVENTION

In FIG. 1 there is shown the laser scanning system LSS which includes a clock generator CG for controlling the operation of the system. When the system is in a writing mode, the laser LZ projects a beam of light via the optical modulator OM to the oscillating torsion rod mirror OTR from whence it is deflected to the record medium RM. The oscillating torsion rod OTR is a conventional device which, when a voltage is applied to mirror drive MD, will oscillate about a rest position. Typically, the amplitude of the oscillations is in the order of three degrees. Thus, if the record medium RM moves in a vertical direction, a series of parallel lines can be traced by a continuously operating laser LZ. However, under normal circumstances, the optical modulator OM is controlled to block and pass the light beam in a pattern controlled by a character generator, not shown. In this way, dot patterns can be made to form graphic patterns. While the system as shown concerns the recording of characters on a record medium, it is equally possible to use the system to scan characters previously recorded on the record medium. In this case, the laser would be continuously on and scanning in the same manner as for writing. However, the system would further include a photo-electric means aimed at the scanning path to pick up reflections therefrom. Furthermore, the relative positions of the record medium, the mirror and the laser are purely representative. In addition, the movement of the record medium to permit the generation of parallel lines is merely by way of example. It is also possible to use a fixed record medium and carry the laser-modulator-torsion rod mirror system on a carriage and move this carriage with respect to the record medium. In any event, the recording and scanning parts of the system do not concern the present invention. The present invention is concerned with the generation of the working clock pulses fed on the line WCK to the optical modulator OM to insure that any dot patterns that are recorded are uniformly spaced along a scan line.

To accomplish this, the clock generator GC is employed, along with a second optical path. In particular, the beam from the laser is reflected off half-silvered mirror FM1 to mirror FM2 and from there via mirror FM3 to the reverse side of the oscillating torsion rod mirror OTR. The light beam is then reflected off this reverse side and actually sweeps out an arc of approximately 3°. Somewhere along that portion of the arc is positioned a photo detector PD. The photo detector PD is aimed at an intermediate point in the arc and not at the end points. Thus, during each cycle of oscillation the photo detector PD picks up two light pulses. These light pulses are fed to divide-by-two counter DB2 so that one (fiducial) pulse occurs for each complete cycle of oscillation of the galvanometer mirror OGM. In response thereto, the frequency synthesizer FZ generates radio-frequency clock pulses which has a frequency much higher than the frequency of the fiducial pulses. In fact, the multiplication factor in frequency can be in the order of two to the eleventh power. The radio frequency clock pulses are emitted on the line RFC. In addition, the frequency synthesizer FZ emits on line CVS two start of sweep pulses per cycle of oscillation of the galvanometer mirror. These two sweep pulses are precisely 180° apart in the oscillatory pattern of the mirror. As can be seen in FIG. 2, the oscillatory pattern is a sinesoid swinging about a rest or center position. The two start of scan pulses are picked so that they occur somewhat after a change in direction of the movement of the mirror. Shown in FIG. 2, one of these pulses occurs at point VS1 and the other at point VS2. Preferably, these pulses are picked to occur at about from 15° to 20° from the end points of the travel so that the highly non-linear portions of the oscillation are not used. (The gross location of these points is established by the photodetector PD.) In any event, each pulse on line CVS sets the flipflop FF which opens the address generator AG1. (It should be noted at this time the address generator AG1 is at address 0.) In addition, the setting of the flipflop FF causes a positive going transient to pass through the OR-circuit OR and increment the address generator to the first address. The address is fed to the read-only memory ROM.

In the read-only memory ROM in sequential addresses are stored count values. These count values are obtained by dividing the angular displacement between the point VS1 and E1 in the oscillation into an equal number of angles and thereafter determining the sine value for each one of those angles and then, finally, subtracting adjacent sine values to obtain a difference number. These difference numbers are multiplied by a constant related to the frequency of the radio frequency clock pulses. This final set of numbers determines the count values that are stored in the read-only memory ROM. Thus, for address 1, there is stored the count value between the start of the scan and the first delta theta point. This count value is read from the read-only memory into the programmable down counter PC2. The down counter starts unit decrementing by the receipt of the radio frequency clock pulses on the line RFC. When the down counter reaches an underflow, a pulse is emitted from its output 0 onto the line WCK. This pulse is a working clock pulse. In addition, that pulse is fed through the OR-circuit OR to increment the address generator to address 2. The trailing edge of the pulse on line WCK causes a triggering of the L-input of the programmable counter PC2 and the next value is loaded into the counter. Finally, when the address for the last count value occurs, the address generator AG is driven to overflow. At that time, the pulse from the 0-output resets the flipflop FF and awaits the next start scan pulse on line CVS.

The frequency synthesizer FZ comprises a conventional phase-locked loop consisting of the phase comparator PC having one input connected to receive the fiducial pulses from the divide-by-two DB2. The output of the phase comparator PC is fed to a high-frequency voltage controlled oscillator VCO which generates the radio frequency clock pulses on line RFC. These clock pulses are divided down to the frequency of the fiducial pulses. The dividing is performed by a cascaded divided chain comprising, by way of example, divide-by-four DB4 (which if the frequencies are sufficiently high, must be an emitter-coupled logic device), the divided-by-thirty two DB32 and the divide-by-sixteen DB16 whose output is fed to the other input of the phase comparator PC for comparison with the fiducial pulses.

Under normal circumstances, a tap in the divider chain could be used to generate the start of scan pulses. However, because of mechanical uncertainty in positioning the photodetector PD and the tolerances in the electrical components in the phase-locked loop, it may be necessary to controllably vary the occurrence of the start of scan, i.e. the point VS1 in FIG. 2. In order to provide the facility to vary the start of this point, there is included in th system the programmable counter RC1. The inputs to this counter are an array of parallel switches which, in effect, introduce a coded number or count value into the counter. The counting is performed by pulses on line CK from the divide-by-four DB4. The counter is controlled to operate when particular counts are registered in the divide-by-sixteen DB16. (The three most significant bits therein) This particular count is sensed by the AND-circuit AND which is fed via the line RVS to the load input of the counter PC1. If even further precise control of this start point is needed, one can introduce delay multivibrators in the line CVS with the timing of the multivibrators controlled by a variable potentiometer in their timing circuits.

While only one embodiment of the invention has been shown and described in detail, it will now be obvious to those skilled in the art many modifications and variations satisfying many or all of the objects of the invention without departing from the spirit thereof. For example, instead of using the programmable down counter PC, one could equally well use a regular up-counter and feed the output of this up-counter into one side of a parallel comparator whose other side receives count values from the read-only memory ROM so that when the equalities occur, the output of the comparator generates the pulses on line WCK which are used to select the next count value from the memory.

Другие статьи, обзоры программ, новости

Verilog for Verification

$display ( "End of simulation time is %d. total number of clocks seen is %d expected is %d". $time. no_of_clocks ,( $time / 5 ));

End of simulation time is 50000. total number of clocks seen is 12500 expected is 10000

Total number of clocks are 12500 and the expected are 1000.There are 25 % of more clocks than expected. The reason is half clock period is 2 insted of 2.5.

Make sure that CLOCK_PERIOD is evenly divided by two. If CLOCK_PERIOD is odd, the reminder is truncated the frequency of the clock generated in not what expected. If integer division is replaced by real division, the result is rounded off according to the specified resolution.

module Tb ();

initial no_of_clocks = 0 ;

initial clock = 1'b0 ;

always #( CLOCK_PERIOD / 2.0 ) clock =

$display ( "End of simulation time is %d. total number of clocks seen is %d expected is %d". $time. no_of_clocks ,( $time / 5 ));

End of simulation time is 50000. total number of clocks seen is 8333 expected is 10000

Look at the result, total number of clock seen are 8333, where the rest of the clocks have gone? There is some improvement than earlier example. But the results are not proper. Well that is because of `timeprecision. By default time precision is 1ns/1ns. Half of the clock period is 2.5. It is rounded of to 3. So total time period is 6 and resulted 8333 clocks( 50000/6) instead of (50000/5). 2.5 can be rounded to 3 or 2. LRM is specific about this. So try out this example on your tool. You may see 12500.

Timescale And Precision Enlightment:

Delay unit is specified using 'timescale, which is declared as `timescale time_unit base / precision base

--time_unit is the amount of time a delay of 1 represents. The time unit must be 1 10 or 100

--base is the time base for each unit, ranging from seconds to femtoseconds, and must be: s ms us ns ps or fs

--precision and base represent how many decimal points of precision to use relative to the time units.

Time precision plays major role in clock generators. For example, to generate a clock with 30% duty cycle and time period 5 ns ,the following code has some error.

`timescale 1ns / 100ps

module Tb ();

reg clock ;

integer no_of_clocks ;

parameter CLOCK_PERIOD = 5 ;

initial clock = 1'b0 ;

#( CLOCK_PERIOD / 3.0 ) clock = 1'b0 ;

$display ( " End of simulation time is %d. total number of clocks seen is %d expected is %d". $time. no_of_clocks ,( $time / 5 ));

End of simulation time is 50000. total number of clocks seen is 9999 expected is 10000

Now CLOCK_PERIOD/3.0 is 5/3 which is 1.666. As the time unit is 1.0ns, the delay is 1.666ns. But the precision is 100ps. So 1.666ns is rounded to 1.700ns only.

and when (CLOCK_PERIOD - CLOCK_PERIOD/3.0) is done, the delay is 3.300ns instead of 3.333.The over all time period is 5.If the clock generated is implemented without taking proper care, this will be the biggest BUG in testbench.

All the above clock generators have hard coded duty cycle. The following example shows the clock generation with parameterizable duty cycle. By changing the duty_cycle parameter, different clocks can be generated. It is beneficial to use parameters to represent the delays, instead of hard coding them. In a single testbench, if more than one clock is needed with different duty cycle, passing duty cycle values to the instances of clock generators is easy than hard coding them.

NOTE: Simulation with `timescale 1ns/1ns is faster than `timescale 1ns/10ps

A simulation using a `timescale 10ns/10ns and with `timescale 1ns/1ns will take same time.

parameter CLK_PERIOD = 10 ;

parameter DUTY_CYCLE = 60 ; //60% duty cycle

parameter TCLK_HI = ( CLK_PERIOD * DUTY_CYCLE / 100 );

parameter TCLK_LO = ( CLK_PERIOD - TCLK_HI );

Clock generator

Clock generator

A laptop PC clock generator, based on the Seligo chip

A clock generator is a circuit that produces a timing signal (known as a clock signal and behaves as such) for use in synchronizing a circuit's operation. The signal can range from a simple symmetrical square wave to more complex arrangements. The basic parts that all clock generators share are a resonant circuit and an amplifier.

The resonant circuit is usually a quartz piezo-electric oscillator. although simpler tank circuits and even RC circuits may be used.

The amplifier circuit usually inverts the signal from the oscillator and feeds a portion back into the oscillator to maintain oscillation.

The generator may have additional sections to modify the basic signal. The 8088 for example, used a 2/3 duty cycle clock, which required the clock generator to incorporate logic to convert the 50/50 duty cycle which is typical of raw oscillators.

Other such optional sections include frequency divider or clock multiplier sections. Programmable clock generators allow the number used in the divider or multiplier to be changed, allowing any of a wide variety of output frequencies to be selected without modifying the hardware.

The clock generator in a motherboard is often changed by computer enthusiasts to control the speed of their CPU, FSB, GPU and RAM. Typically the programmable clock generator is set by the BIOS at boot time to the value selected by the enthusiast; although some systems have dynamic frequency scaling that frequently re-program the clock generator.

Timing Signal Generators (TSGs)

TSGs are clocks that are used throughout service provider networks, frequently as the Building Integrated Timing Supply (BITS) for a central office.

Digital switching systems and some transmission systems (e.g. SONET) depend on reliable, high-quality synchronization (or timing) to prevent impairments. To provide this, most service providers utilize interoffice synchronization distribution networks based on the stratum hierarchy, and implement the BITS concept to meet intraoffice synchronization needs.

A TSG is clock equipment that accepts input timing reference signals and generates output timing reference signals. The input reference signals can be either DS1 or Composite Clock (CC) signals, and the output signals can also be DS1 or CC signals (or both). A TSG is made up of the six components listed below:

  • An input timing interface that accepts DS1 or CC input signals
  • A timing generation component that creates the timing signals used by the output timing distribution component
  • An output timing distribution component that utilizes the timing signals from the timing generation component to create multiple DS1 and CC output signals
  • A Performance Monitoring (PM) component that monitors the timing characteristics of the input signals
  • An alarm interface that connects to the Central Office (CO) alarm monitoring system
  • An operations interface for local craftsperson use and communications with remote operations systems.

Clock generator - Patent application

Inventors: Masaki Sano (Kanagawa, JP)

A multiphase clock with high resolution is generated. A first clock generator circuit (120) includes n level converters BUFs that conduct level conversion on two input signals, and generate a pair of pulse signals that switch the levels with reference to a crossing point at which the two signal are identical in level with each other. An i-th BUF in the first clock generator circuit (120) inputs a one-side output pair that is respective one-side outputs of the differential outputs of two i-th (1≦i≦n) and (i+1)-th (1 when i=n) differential circuits in a ring oscillator 110 in which n differential circuits DCELs having differential inputs and outputs are connected in a ring configuration. The one-side output pair is two one-side outputs that are input to the noninverting terminal of the next differential circuit, or the two one-side outputs that are input to the inverting terminal of the next differential circuit.

1. A clock generator comprising:a ring oscillator having a plurality of differential circuits coupled together in a series, each differential circuit having a differential input and a differential output, said differential output of one circuit being coupled to said differential input of a next one of said circuits in said plurality of circuits, said plurality of circuits having a FIRST circuit and a LAST circuit, said differential output of said LAST circuit being coupled to said differential input of said FIRST circuit, said plurality of circuits comprising an EVEN subplurality of differential circuits and an ODD subplurality of differential circuits alternately coupled with each other in said series, said plurality of differential circuits arranged and configured to produce an ODD number of inversions of a signal in one pass through said plurality of differential circuits; and a level converter receiving two input signals, generating an output signal and providing a characteristic between said output signal and a difference between said two input signals, said characteristic having an odd function being geometrically symmetric with respect to a crossing point of same level between said two input signals, one of said two input signals revealed to said output from one of said differential circuits of said ODD subplurality, the other one of said two input signals revealed to said output from one of said differential circuits of said EVEN subplurality.

2. The clock generator according to claim 1,wherein the ring oscillator includes a differential input pair of lines provided on said input of each delay circuit and a differential output pair of lines provided on said output of each said delay circuit, said differential output pair of lines provided on one circuit being CASCADEDLY coupled to said differential input pair of lines provided on a next one of said circuits in said plurality of circuits.

3. The clock generator according to claim 2,wherein the one of said two input signals is revealed to one of said output pair of lines provided on said output from one of said differential circuits of said ODD subplurality and the other one of said two input signals is revealed to one of said output pair of lines provided on said output from one of said differential circuits of said EVEN subplurality.

4. The clock generator according to claim 3,wherein the one of said differential circuits of said ODD subplurality is sequentially adjacent to the one of said differential circuits of said EVEN subplurality.

5. The clock generator according to claim 2,wherein the number of said circuits comprising said plurality of differential circuits is an EVEN number.

6. The clock generator according to claim 5,Wherein the differential output pair of lines provided on said output of said LAST circuit is CROSS-COUPLED to the differential input pair of lines provided on said input of said FIRST circuit to arrange and configure to produce an ODD number of inversions of a signal in one pass through said plurality of differential circuits.

7. The clock generator according to claim 6,wherein the one of said two input signals is revealed to its one of said differential output pair of lines provided on said output of said LAST circuit and the other one of said two input signals is revealed to its other one of said differential output pair of lines provided on said input of said FIRST circuit.

8. The clock generator according to claim 2,wherein the number of said circuits comprising said plurality of differential circuits is an ODD number.

9. The clock generator according to claim 8,Wherein the differential output pair of lines provided on said output of said LAST circuit is CASCADEDLY COUPLED to the differential input pair of lines provided on said input of said FIRST circuit to arrange and configure to produce an ODD number of inversions of a signal in one pass through said plurality of differential circuits.

10. The clock generator according to claim 9,wherein the one of said two input signals is revealed to its one of said differential output pair of lines provided on said output of said LAST circuit and the other one of said two input signals is revealed to its one of said differential output pair of lines provided on said input of said FIRST circuit.

11. A clock generator comprising:a ring oscillator having a plurality of inverting delay circuits coupled together in a cascaded series, each delay circuit having an input and an output, said output of one delay circuit coupled to said input of a next sequential one of said delay circuits, said plurality of delay circuits comprising a cascaded series, said cascaded series having a FIRST delay circuit and a LAST delay circuit, said LAST delay circuit having its output coupled to said input of said FIRST delay circuit, said cascaded series of delay circuits comprising an ODD subplurality of delay circuits and an EVEN subplurality of delay circuits alternately coupled in sequence to each other; anda level converter receiving two input signals, generating an output signal and providing a characteristic between said output signal and a difference between said two input signals, said characteristic having an odd function being geometrically symmetric with respect to a crossing point of same level between said two input signals, one of said two input signals revealed to said output from one of said delay circuits of said ODD subplurality, the other one of said two input signals revealed to said output from one of said delay circuits of said EVEN subplurality.

Description:

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a clock generation technique, and more particularly, to a technique of generating a plurality of clocks that are different in phase from each other.

[0003] 2. Description of the Related Art

[0004] In recent years, there has spread an information recording device which irradiates an optical disc medium such as a compact disc (CD) or a digital versatile disc (DVD) with a laser beam that is emitted according to a recording pulse signal (recording clock) which is generated by a phase locked loop (PLL) circuit to record information. In the actual recording operation of the information recording device, in order to determine a recording position on an optical disc with a high precision, a cycle shorter than a cycle of the recording clock, for example, a clock of 1/16 or 1/32 of the cycle of the recording clock is used, and a higher recording quality is obtained as the cycle is shorter, that is, the resolution is higher.

[0005] There have been proposed various techniques for obtaining the clock that is high in resolution. For example, JP2006-294131 A discloses a technique of shifting the phase of the reference clock little by little to generate a multiphase clock. Although JP 2006-294131 A fails to suggest how to shift the phase of the reference clock, there is assumed that a plurality of differential circuits that are sequentially connected to each other are used. According to the technique, it is possible to obtain the resolution corresponding to the amount of delay of one differential circuit.

[0006] Also, there has been known a technique of using a multiphase clock consisting of outputs of the respective stages of a ring oscillator that is normally used in a voltage controlled oscillator (VCO) of a PLL circuit. For example, JP 2000-156629 A discloses a technique of obtaining a clock output having a resolution higher than the amount of delay of n (n is an integer of 2 or larger) differential circuits by the aid of a first ring oscillator and a second ring oscillator having the differential circuits connected in a ring configuration. In the technique, the output of an i-th (1≦i≦n) differential circuit of the second ring oscillator is phase-coupled with the output of an i-th differential circuit of the first ring oscillator, and the output of the i-th (1≦i≦n) differential circuit of the second ring oscillator is phase-coupled with the output of an (i+1)-th (1 when i=n) differential circuit of the first ring oscillator. With the above configuration, the output signal of the i-th differential circuit of the second ring oscillator has an intermediate phase between the phases of the outputs of the i-th differential circuit and the (i+1)-th differential circuit in the first ring oscillator. That is, the first ring oscillator and the second ring oscillator maintain oscillations in a state where their phases are temporally shifted by 1/2 of the amount of delay of the differential circuits that constitute the first ring oscillator and the second ring oscillator. As a result, a time interval of the phase state during the oscillation becomes as fine as 1/2 of the amount of delay of the differential circuits, thereby making it possible to increase the resolution of the oscillator circuit to twice of a limit that is determined by the amount of delay of the differential circuits.

[0007] There has been known the ring oscillator of VCO which is made up of differential circuits having differential input and output. FIG. 5 shows an example of the ring oscillator in which the four differential circuits DCELs (DCEL1 to DCEL4) are disposed. Each of the DCELs inverts the phase of a pair of input signals that are differential outputs of a previous DCEL, and outputs the inverted signals to a next DCEL with a delay of a given time (delay amount t). In the ring oscillator, the differential input and the differential output of each DCEL have the same cycle T (in the example shown, the cycle T is "8Г—t" because the number of DCELs is four).

[0008] When the above ring oscillator is designed in such a manner that the differential outputs of the respective DCELs are converted in level by the aid of a level converter to obtain the clock signal, the multiphase clock can be obtained.

[0009] FIG. 6 shows a clock that can be obtained by subjecting the differential outputs ON1 and OP1 of the DCEL1 and clocks that can be obtained by converting the differential outputs ON1 and OP1 in level. As shown in the figure, ON1 and OP1 are a pair of sine waves that are opposite in phase to each other, and have the same level and cross each other at a point of "TГ—1/2". As a result of converting the levels of ON1 and OP1, a pair of clocks that are opposite in phase to each other can be obtained, and those clocks switch their levels at a point (crossing point) where ON1 and OP1 cross each other.

[0010] Likewise, when the levels of ON2 and OP2, ON3 and OP3, and ON4 and OP4 are converted, respectively, the clocks shown in FIG. 6 can be obtained from the differential outputs of the respective DCELs. Since the outputs of the respective DCELs are sequentially delayed by the delay amount t, the clocks that are obtained by converting the differential outputs of the respective DCELs in level are also sequentially shifted in phase by the delay amount t. The clocks of eight phases can be generated from the outputs of the respective DCELs of the ring oscillator shown in FIG. 5 in the above manner.

[0011] The multiphase clocks that are generated by converting the levels of the outputs of the respective DCELs of the ring oscillator which is constituted by the DCELs having the differential inputs and outputs as shown in FIG. 5 are sequentially shifted in phase by the delay amount t of the DCELs, thereby making it impossible to obtain the resolution that is equal to or higher than a resolution corresponding to the delay amount t of the DCELs. In order to obtain the resolution that is equal to or higher than the resolution corresponding to the delay amount t of the DCELs, it is necessary to generate a clock having a phase between the phases of clocks which are generated from the outputs of two adjacent DCELs.

[0012] One aspect of the present invention resides in a clock generator. The clock generator includes: a ring oscillator having a plurality of differential circuits coupled together in a series, each differential circuit having a differential input and a differential output, the differential output of one circuit being coupled to the differential input of a next one of the circuits in the plurality of circuits, the plurality of circuits having a first circuit and a last circuit, the differential output of the last circuit being coupled to the differential input of the first circuit, the plurality of circuits including an even subplurality of differential circuits and an odd subplurality of differential circuits alternately coupled with each other in the series, the plurality of differential circuits arranged and configured to produce an odd number of inversions of a signal in one pass through the plurality of differential circuits; and a level converter receiving two input signals, generating an output signal and providing a characteristic between the output signal and a difference between the two input signals, the characteristic having an odd function being geometrically symmetric with respect to a crossing point of same level between the two input signals, one of the two input signals revealed to the output from one of the differential circuits of the odd subplurality, the other one of the two input signals revealed to the output from one of the differential circuits of the even subplurality.

[0013] The above clock generator can be replaced and represented by a device, a method, or a system, which is effective as other aspects of the present invention.

[0014] According to the technique of the present invention, when the multiphase clocks are generated by the aid of the outputs of the respective DCELs in the ring oscillator that is constituted by the DCELs having the differential inputs, it is possible to generate a clock having a phase between the phases of clocks which are generated from the outputs of two adjacent DCELs.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG. 1 is a diagram showing a clock generator according to an embodiment of the present invention;

[0016] FIG. 2 is a diagram showing the outputs of respective differential circuits of a ring oscillator in the clock generator shown in FIG. 1;

[0017] FIG. 3 is a diagram for explaining a first clock generator circuit and a second clock generator circuit in the clock generator shown in FIG. 1;

[0018] FIG. 4 is a diagram showing multiphase clocks that are generated by the clock generator shown in FIG. 1;

[0019] FIG. 5 is a diagram showing an example of the ring oscillator that is constituted by the differential circuits having differential inputs and outputs; and

[0020] FIG. 6 is a diagram for explaining a method of generating the multiphase clocks by the aid of the outputs of the respective differential circuits in the ring oscillator shown in FIG. 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0021] FIG. 1 is a clock generator 100 according to an embodiment of the present invention. The clock generator 100 includes a ring oscillator 110, a first clock generator circuit 120, and a second clock generator circuit 130.

[0022] The ring oscillator 110 is a ring oscillator used for a VCO of a PLL circuit, and in the ring oscillator 110, a plurality of, in this example, four differential circuits DCELs (DCEL1 to DCEL4) are connected in a ring configuration, and each of the differential circuits DCELs has a differential input and a differential output.

[0023] The second clock generator circuit 130 includes four level converters BUFs (BUF11 to BUF14) that input the outputs (differential outputs) of the respective DCELs in the ring oscillator 110, respectively, and conduct level conversion on the input signals to generate and output a pair of pulse signals (clocks).

[0024] Similarly, the first clock generator circuit 120 also has four level converters BUFs (BUF21 to BUF24), and each of the BUFs inputs the respective one of the differential outputs of two adjacent DCELs in the ring oscillator 110, and conducts level conversion on the input signals to generate and output a pair of clocks.

[0025] In the ring oscillator 110, the DCEL1 inverts the phases of signals that are input to a noninverting terminal and an inverting terminal, respectively, and outputs differential signals ON1 and OP1 with a delay of a given period (delay amount t). The signal ON1 corresponds to a signal that is input to the noninverting terminal of the DCEL1, and the signal OP1 corresponds to a signal that is input to the inverting terminal of the DCEL1. In the following description, in the input and output of the DCEL, the signal that is input to the noninverting terminal is called "noninverting input", and an output signal corresponding to the input signal is called "noninverting output". Also, the signal that is input to the inverting terminal is called "inverting input", and an output signal corresponding to the input signal is called "inverting output".

[0026] The noninverting output ON1 of the DCEL1 is input to the noninverting terminal of the DCEL2, and inverted and delayed by the DCEL2 to generate ON2 which is input to the noninverting terminal of the DCEL3 as the noninverting output of the DCEL2. Then, ON2 is input to the noninverting terminal of the DCEL3 and inverted and delayed by the DCEL3 to generate ON3 which is input to the noninverting terminal of the DCEL4 as the noninverting output of the DCEL3.

[0027] The inverting output OP1 of the DCEL1 is input to the inverting terminal of the DCEL2, and inverted and delayed by the DCEL2 to generate OP2 which is input to the inverting terminal of the DCEL3 as the inverting output of the DCEL2. Then, the OP2 is input to the inverting terminal of the DCEL3 and inverted and delayed by the DCEL3 to generate OP3 which is input to the inverting terminal of the DCEL4 as the inverting output of the DCEL3.

[0028] The DCEL 4 inverts and delays the phase of the noninverting input ON3 to obtain the noninverting output ON4, and also inverts and delays the inverting input OP3 to obtain the inverting output OP4. The noninverting output ON4 and the inverting output OP4 of the DCEL4 are input to the inverting terminal and the noninverting terminal of the DCEL1, respectively. The respective DCELs have the same delay amount t.

[0029] FIG. 2 shows outputs from the respective differential circuits of the ring oscillator 110. One scale in a time axial direction in the figure indicates the delay amount t of the DCEL. As shown in the figure, the output of each of the DCELs is generated by inverting in phase and delaying by the delay amount t with respect to the output of the previous DCEL, and the cycle of the output signals from the respective DCELs has the same T. The cycle T is equal to eight times as large as the delay amount t.

[0030] The BUF11 to BUF14 in the second clock generator circuits input the ON1/OP1 to ON4/OP4 shown in FIG. 2, respectively, and conduct level conversion on the ON1/OP1 to ON4/OP4. Since the respective BUFs conduct the same operation except that the input signals are different, the BUF11 and BUF12 will be exemplified with reference to FIG. 3. The respective BUFs that conduct the level conversion generate a pair of pulse signals that switch the levels on the basis of a point (crossing point) at which the two input signals become identical with each other in level, and a distance between the point at which the level switches and the crossing point depends on the amount of delay of the BUF. In the following description and drawing, for facilitation of understanding the main feature of the present invention, the delay of the BUF is omitted, and the each of the BUFs generate a pair of pulse signals that switch the levels at the crossing point of the two input signals.

[0031] The BUF11 inputs the noninverting output ON1 and the inverting output OP1 of the DCEL1, and conducts the level conversion on the input signals to obtain output signals indicated by CK11A and CK11B in FIG. 3. The CK11A and the CK11B are a pair of clocks that are opposite in phase to each other, and the levels of the CK11A and the CK11B switch at the crossing point of the ON1 and OP1. Since the ON1 and the OP1 have the same cycle T and the phases opposite to each other, the ON1 and the OP1 cross each other and become identical in the level with each other at the points of the integer multiple of "TГ—1/2". Accordingly, CK11A and CK11B have the cycle T, and switch the level at the points of the integer multiple of "TГ—1/2".

[0032] The BUF12 inputs the noninverting output ON2 and the inverting output OP2 of the DCEL2, and conducts the level conversion on the input signals to obtain output signals indicated by CK12A and CK12B in FIG. 3. The CK12A and the CK12B are a pair of clocks that are opposite in phase to each other, and the levels of the CK12A and the CK12B switch at the crossing point of the ON2 and OP2.

[0033] As is understood from FIG. 3, the four clocks CK11A, CK11B, CK12A, and CK12B have the same cycle, the CK11A and the CK11B are opposite in phase to each other, and the CK12A and the CK12B are opposite in phase to each other. Also, the CK12A is delayed from the CK11A by the delay amount t, and the CK12B is delayed from the CK12A by the delay amount t.

[0034] Also, although being not shown in FIG. 3, the BUF13 and the BUF14 also conduct the level conversion on the ON3 and the OP3, and the ON4 and the OP4, respectively to obtain the clocks CK13A and CK13B, and the clocks CK14A and CK14B. The CK13A and the CK13B are opposite in phase to each other, and the CK14A and the CK14B are opposite in phase to each other. Also, the CK13A is delayed from the CK12A by the delay amount t, and the CK14A is delayed from the CK13A by the delay amount t. Likewise, the CK13B is delayed from the CK12B by the delay amount t, and the CK14B is delayed from the CK13B by the delay amount t.

[0035] That is, the second clock generator circuit 130 can obtain the clocks of eight phases in total, and has the resolution corresponding to the delay amount t of the DCEL in the ring oscillator 110.

[0036] A relationship between the outputs of the two adjacent DCELs in the ring oscillator 110 will be described before the first clock generator circuit 120 will be described in detail. In this example, the DCEL1 and DCEL2 will be described.

[0037] As has been described above, because the ON1 and the OP1 have the same cycle T and are opposite in phase to each other, the ON1 and the OP1 cross each other at the points of the integer multiple of "TГ—1/2". On the other hand, as shown by "the ON1 and the ON2" in FIG. 3, because the noninverting output ON2 of the DCEL2 is a signal obtained by inverting the noninverting output ON1 of the DCEL1 and delaying the inverted noninverting output ON1 by the delay amount t, the ON2 and the ON1 cross each other at the points of "an integer multiple of (TГ—1/2)+tГ—1/2".

[0038] Likewise, as shown by "the OP2 and the OP1" in FIG. 3, because the inverting output OP2 of the DCEL2 is a signal obtained by inverting the inverting output OP1 of the DCEL1 and delaying the inverted inverting output OP1 by the delay amount t, the OP2 and the OP1 cross each other at the points of "an integer multiple of (TГ—1/2)+tГ—1/2".

[0039] Also, although being not shown in FIG. 3, because the noninverting output ON3 of the DCEL3 is a signal obtained by inverting the noninverting output ON2 of the DCEL2 and delaying the inverted noninverting output ON2 by the delay amount t, the ON3 and the ON2 cross each other at the points of "an integer multiple of (TГ—1/2)+tГ— 3/2". The same is applied to the inverting output OP3 of the DCEL3 and the inverting output OP2 of the DCEL2.

[0040] Likewise, the noninverting output ON4 of the DCEL4 and the noninverting output ON3 of the DCEL3, or the inverting output OP4 of the DCEL4 and the inverting output OP3 of the DCEL3 cross each other at the point of "an integer multiple of (TГ—1/2)+tГ— 5/2".

[0041] The noninverting output ON4 of the DCEL4 is input to the inverting terminal of the next DCEL1, and the inverting output OP4 is input to the noninverting terminal of the DCEL1. For that reason, the noninverting output ON1 of the DCEL1 and the inverting output OP4 of the DCEL4, or the inverting output OP1 of the DCEL1 and the noninverting output ON4 of the DCEL4 cross each other at the point of "an integer multiple of (TГ—1/2)+tГ— 7/2".

[0042] The first clock generator circuit 120 will be described given the above relationship between the outputs of the two adjacent DCELs in the ring oscillator 110.

[0043] The first clock generator circuit 120 also has four level converters BUFs (BUF21 to BUF24), and each of the BUFs has the same function as that of the respective BUFs in the second clock generator circuit 130.

[0044] The BUF21 inputs the inverting output OP2 of the DCEL2 and the inverting output OP1 of the DCEL1 to generate a pair of clocks CK21A and CK21B that are opposite in phase to each other. Because the OP2 and the OP1 cross each other at the points of "an integer multiple of (TГ—1/2)+tГ—1/2", as shown in FIG. 3, the CK21A and the CK21B switch the levels at the points of "an integer multiple of (TГ—1/2)+tГ—1/2".

[0045] As is understood from the comparison of the clock CK21A that is output by the BUF21 with the clock CK11A that is output by the BUF11, the CK21A is delayed from the CK11A by "tГ—1/2". Also, the CK21B is delayed from the CK11B by "tГ—1/2".

[0046] The BUF22 inputs the noninverting output ON3 of the DCEL3 and the noninverting output ON2 of the DCEL2 to generate a pair of clocks CK22A and CK22B that are opposite in phase to each other. As described above, because the ON3 and the ON2 cross each other at the points of "an integer multiple of (TГ—1/2)+tГ— 3/2", the CK22A and the CK22B switch the levels at the points of "an integer multiple of (TГ—1/2)+tГ— 3/2".

[0047] That is, the clock CK22A that is output by the BUF22 is delayed from the clock CK21A that is output by the BUF21 by the delay amount t, and the CK22B is also delayed from the CK21B by the delay amount t.

[0048] The BUF23 inputs the inverting output OP4 of the DCEL4 and the inverting output OP3 of the DCEL3 to generate a pair of clocks CK23A and CK23B that are opposite in phase to each other. As described above, because the OP4 and the OP3 cross each other at the points of "an integer multiple of (TГ—1/2)+tГ— 5/2", the CK23A and the CK23B switch the levels at the points of "an integer multiple of (TГ—1/2)+tГ— 5/2".

[0049] That is, the clock CK23A that is output by the BUF23 is delayed from the clock CK22A that is output by the BUF22 by the delay amount t, and the CK23B is also delayed from the CK22B by the delay amount t.

[0050] The BUF24 inputs the noninverting output ON1 of the DCEL1 and the inverting output OP4 of the DCEL4 to generate a pair of clocks CK24A and CK24B that are opposite in phase to each other. As described above, because the ON1 and the OP4 cross each other at the points of "an integer multiple of (TГ—1/2)+tГ— 7/2", the CK24A and the CK24B switch the levels at the points of "an integer multiple of (TГ—1/2)+tГ— 7/2".

[0051] That is, the clock CK24A that is output by the BUF24 is delayed from the clock CK23A that is output by the BUF23 by the delay amount t, and the CK24B is also delayed from the CK23B by the delay amount t.

[0052] The first clock generator circuit 120 obtains the clocks of eight phases in total. Since the second clock generator circuit 130 also obtains the clocks of eight phases in total, the clock generator 100 generates the clocks of 16 phases in total.

[0053] FIG. 4 shows the clocks of 16 phases which are generated by the clock generator 100. The clocks of eight phases (CK11A/CK11B to CK14A/CK14B) of an upper portion of FIG. 4 are generated by the second clock generator circuit 130, and the clocks of eight phases (CK21A to CK24A and CK21B to CK24B) of a lower portion are generated by the first clock generator circuit 120. The CK11A, CK21A, CK12A, CK22A, CK13A, CK23A, CK14A, and CK24A are sequentially delayed by "delay amount tГ—1/2", and CK11B, CK21B, CK12B, CK22B, CK13B, CK23B, CK14B, and CK24B that are inverting signals of CK11A, CK21A, CK12A, CK22A, CK13A, CK23A, CK14A, and CK24A, respectively, are also sequentially delayed by "delay amount tГ—1/2". That is, the clock generator 100 shown in FIG. 1 obtains the resolution corresponding to 1/2 of the delay amount t of the DCELs that constitute the ring oscillator 110.

[0054] As described above, in the clock generator 100 according to this embodiment, the level converters BUFs of the first clock generator circuit 120 input the respective one of the differential outputs of the two adjacent DCELs in the ring oscillator 110 and conduct the level conversion on the input signals, to thereby obtain the clocks having the intermediate phase of the clock which is obtained by the two level converters BUF in the second clock generator circuit 130 which input the differential outputs of the two DCELs, respectively, to conduct the level conversion on the input signals. Accordingly, it is possible to realize the resolution of twice as large as the resolution corresponding to the delay amount t of the differential circuits in the ring oscillator 110.

[0055] In the structure that input the respective outputs in the ring oscillator that is constituted by the DCELs having the differential inputs and outputs, and conduct the level conversion on the input signals, in order to obtain the same resolution as that of the clock generator in the embodiment shown in FIG. 1, it is necessary to design the amount of delay of the DCELs in half. In order to halve the amount of delay of the DCELs, it is necessary to at least double the current that drives the DCELs, which is disadvantageous from the viewpoint of the current consumption. On the contrary, in this embodiment, the first clock generator circuit 120 that is constituted by the level converters that are smaller in the current consumption than the DCELs is added to realize the high resolution. As a result, it is possible to suppress the current consumption.

[0056] Also, in the method disclosed in JP2000-156629A, in order to obtain the resolution that is equal to or higher than a limit resolution which is determined by the amount of delay of the differential circuits, it is necessary that the output of the i-th (1≦i≦n) differential circuit of the second ring oscillator which is referred to in JP 2000-156629 A is combined in phase with the output of the i-th differential circuit of the first ring oscillator to take synchronization, which is complicated in circuit. On the contrary, the clock generator according to the present invention can realize the high resolution with the simple circuit structure.

[0057] The present invention has been described above with reference to the embodiment. The embodiment is exemplary, and various changes, increase/decrease, or combination may be made with respect to the embodiment described above without departing from the scope of the invention. It would be obvious by the ordinary skilled men that modified examples that are subjected to the changes, increase/decrease, or combination also fall within the scope of the present invention.

[0058] For example, in the clock generator 100 according to the embodiment shown in FIG. 1, as an example, the ring oscillator 110 has a four-stage configuration, and the first clock generator circuit 120 and the second clock generator circuit 130 also have the four-stage configuration in correspondence with the ring oscillator 110. However, the number of ring oscillator and the number of respective clock output circuits are not limited to four, but can be an arbitrary number of 2 or larger.

[0059] Also, in the clock generator 100 according to the embodiment shown in FIG. 1, the BUF21 in the first clock generator circuit 120 inputs the noninverting output ON2 of the DCEL2 and the noninverting output ON1 of the DCEL1. Alternatively, the BUF21 can input the inverting output OP2 of the DCEL2 and the inverting output OP1 of the DCEL1. That is, the respective BUFs in the first clock generator circuit 120 can input the two one-side outputs of the differential outputs of the corresponding i-th (i is an integer of 1 or larger) stage and (i+1)-th (1 when i=4, and so on) stage, which are input to the noninverting terminals of the next DCEL, respectively, or can be input the two one-side outputs that are input to the next inverting terminal, respectively.